This invention relates to a structure of a capacitor section of a dynamic random-access memory.
As the semiconductor manufacturing technology evolves, the integration density of semiconductor devices is progressively increasing. The higher the integration density of a dynamic random-access memory (hereinafter referred to as "DRAM"), the larger the storage capacity (the number of bits) of the memory, and the smaller the area which each memory cell (one bit) occupies on the semiconductor substrate.
To reduce the area each memory cell occupies, it is necessary to decrease the sizes of the MOS transistor and capacitor which constitute the memory cell. The capacitor incorporated in each memory cell of the DRAM must maintain its capacitance at tens of fF's, no matter how much the area the memory cell occupies is reduced.
Various types of capacitors have been developed for use in the memory cells of DRAMs. One is a stacked type which have storage electrodes (or storage nodes) stacked one above another on a semiconductor substrate. Another is a trench type which has a storage electrode formed in a trench made in a semiconductor substrate and which has a three-dimensional structure.
The stacked type capacitor has a trench in each interlayer insulator provided on the semiconductor substrate. One storage electrode is formed on the sides and bottom of the trench and has an area greater and, hence, a larger capacitance, than otherwise. (See, for example, U.S. Pat. No. 5,444,013.)
It is proposed that the capacitor insulating film be made of high-dielectric materials, instead of the conventionally used ones such as silicon oxide and silicon nitride, so that the capacitor may have capacitance sufficiently large. Examples of high-dielectric materials are: tantalum oxide (Ta.sub.2 O.sub.5), strontium titanate (SrTiO.sub.3, known as "STO"), and barium strontium titanate ((Ba, Sr)TiO.sub.3, known as "BSTO").
An example of a memory cell which has a capacitor film made of high-dielectric material is disclosed in A. Yuuki et al., "International Electron Device Meeting 1995," pages 115 to 118. The capacitor of this memory cell has a simple stacked structure. Its storage electrodes are made of ruthenium and its capacitor insulating film is made of BSTO.
FIG. 1 shows capacitors formed in trenches made in an interlayer insulator. FIG. 2 is a sectional view taken along line II--II in FIG. 1.
The capacitors are arranged on the semiconductor substrate, forming an array. Each capacitor is composed of a storage electrode 53 and a plate electrode 55. The storage electrode 53 is provided on the sides and bottom of the trench 52 made in the interlayer insulator 51. The plate electrode 55 is provided common to all capacitors.
Capacitors of this type are used in the memory cells of DRAMs. Their storage electrodes are connected to one of the source and drain diffusion layers of MOS transistors by contact plugs 50.
As shown in FIGS. 1 and 2, an interlayer insulator 51 isolates any two adjacent capacitors. The recent trend is that the distance d between the capacitors is reduced, increasing the area of each capacitor as much as possible, thereby to prevent the capacitance of each capacitor from decreasing in spite of the reduced size of the memory cells. If the distance d is reduced, however, the leakage current flowing between the adjacent capacitors will increase, or insulation breakdown will occur between the storage electrodes of the adjacent capacitors. If the leakage current increases the insulation breakdown occurs, the capacitors cannot be electrically isolated so sufficiently that the cell may function well enough in DRAMs.